Sr. Hardware Design Engineer (Remote)

We’re looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. This role blends architecture design, hands-on implementation, and technical leadership. You’ll collaborate across engineering teams to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.

Responsibilities

Define HW architecture and evaluate design trade-offs for performance, area, and power.
Lead RTL development, integration, and verification throughout the design cycle.
Partner with firmware and verification teams to ensure top-quality silicon delivery.
Mentor and review junior engineers’ work, promoting best practices and technical excellence.
Provide design-in and bring-up support, including technical expertise for customer-facing projects.

Qualifications

Strong command of SystemVerilog for RTL design and digital architecture.
Experience using simulation tools such as Questa, Incisive, or VCS.
Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
Proven experience in ASIC or FPGA design, synthesis, and timing closure.
Strong analytical thinking and communication skills, with the ability to manage complex priorities.
10+ years of relevant experience and a BSEE or MSEE degree.

Preferred / Plus

Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
Familiarity with UVM-based verification environments.
Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
Understanding of AMBA AXI or CHI protocols.

Details

Location

Remote

Experience

Min. 10 years

Responsibilities

Define HW architecture and evaluate design trade-offs for performance, area, and power.
Lead RTL development, integration, and verification throughout the design cycle.
Partner with firmware and verification teams to ensure top-quality silicon delivery.
Mentor and review junior engineers’ work, promoting best practices and technical excellence.
Provide design-in and bring-up support, including technical expertise for customer-facing projects.

Qualifications

Strong command of SystemVerilog for RTL design and digital architecture.
Experience using simulation tools such as Questa, Incisive, or VCS.
Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
Proven experience in ASIC or FPGA design, synthesis, and timing closure.
Strong analytical thinking and communication skills, with the ability to manage complex priorities.
10+ years of relevant experience and a BSEE or MSEE degree.

Preferred / Plus

Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
Familiarity with UVM-based verification environments.
Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
Understanding of AMBA AXI or CHI protocols.