Sr Staff Engineer, CPU System Microarchitect

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
How to design and optimize a custom RISC-V CPU system from first principles.
Integration of open-source and industry-standard tools to improve RTL flows and results.
Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Details

Location

Hybrid

This role is hybrid, based out of Bengaluru, India.

Who You Are

An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
How to design and optimize a custom RISC-V CPU system from first principles.
Integration of open-source and industry-standard tools to improve RTL flows and results.
Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.